View AD620SQ883B_1118132.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Low Cost Low Power Instrumentation Amplifier AD620
FEATURES
Easy to use Gain set with one external resistor (Gain range 1 to 10,000) Wide power supply range (2.3 V to 18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 V max, input offset voltage 0.6 V/C max, input offset drift 1.0 nA max, input bias current 100 dB min common-mode rejection ratio (G = 10) Low noise 9 nV/Hz @ 1 kHz, input voltage noise 0.28 V p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications 120 kHz bandwidth (G = 100) 15 s settling time to 0.01%
CONNECTION DIAGRAM
RG -IN +IN -VS 1 2 3 4 8 RG
7 +VS 6 OUTPUT
00775-0-001
AD620
TOP VIEW
5 REF
Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages
PRODUCT DESCRIPTION
The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 V max, and offset drift of 0.6 V/C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Supereta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/Hz at 1 kHz, 0.28 V p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 s to 0.01%, and its cost is low enough to enable designs with one in-amp per channel.
10,000
APPLICATIONS
Weigh scales ECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controls Battery-powered and portable equipment
30,000
TOTAL ERROR, PPM OF FULL SCALE
25,000
3 OP AMP IN-AMP (3 OP-07s)
1,000
20,000
RTI VOLTAGE NOISE (0.1 - 10Hz) (V p-p)
TYPICAL STANDARD BIPOLAR INPUT IN-AMP 100 G = 100 10 AD620 SUPERETA BIPOLAR INPUT IN-AMP
15,000
AD620A
10,000 RG
5,000
00775-0-002
1
0 0 5 10 SUPPLY CURRENT (mA) 15 20
0.1 1k
10k
100k 1M SOURCE RESISTANCE ()
10M
100M
Figure 2. Three Op Amp IA Designs vs. AD620 Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 3. Total Voltage Noise vs. Source Resistance
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
00775-0-003
AD620 TABLE OF CONTENTS
Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................5 ESD Caution ..................................................................................5 Typical Performance Characteristics ..............................................7 Theory of Operation .......................................................................13 Gain Selection..............................................................................16 Input and Output Offset Voltage ..............................................16 Reference Terminal .....................................................................16 Input Protection ..........................................................................16 RF Interference............................................................................16 Common-Mode Rejection.........................................................17 Grounding....................................................................................17 Ground Returns for Input Bias Currents.................................18 Outline Dimensions........................................................................19 Ordering Guide ...........................................................................20
REVISION HISTORY
12/04--Rev. F to Rev. G Updated Format.................................................................. Universal Change to Features............................................................................1 Change to Product Description.......................................................1 Changes to Specifications.................................................................3 Added Metallization Photograph....................................................4 Replaced Figure 4-Figure 6 ..............................................................6 Replaced Figure 15 ............................................................................7 Replaced Figure 33 ..........................................................................10 Replaced Figure 34 and Figure 35.................................................10 Replaced Figure 37 ..........................................................................10 Changes to Table 3 ..........................................................................13 Changes to Figure 41 and Figure 42 .............................................14 Changes to Figure 43 ......................................................................15 Change to Figure 44 ........................................................................17 Changes to Input Protection section ............................................15 Deleted Figure 9...............................................................................15 Changes to RF Interference section ..............................................15 Edit to Ground Returns for Input Bias Currents section...........17 Added AD620CHIPS to Ordering Guide ....................................19 7/03--Data Sheet changed from REV. E to REV. F Edit to FEATURES............................................................................1 Changes to SPECIFICATIONS .......................................................2 Removed AD620CHIPS from ORDERING GUIDE ...................4 Removed METALLIZATION PHOTOGRAPH...........................4 Replaced TPCs 1-3 ...........................................................................5 Replaced TPC 12 ...............................................................................6 Replaced TPC 30 ...............................................................................9 Replaced TPCs 31 and 32...............................................................10 Replaced Figure 4 ............................................................................10 Changes to Table I...........................................................................11 Changes to Figures 6 and 7 ............................................................12 Changes to Figure 8 ........................................................................13 Edited INPUT PROTECTION section........................................13 Added new Figure 9........................................................................13 Changes to RF INTERFACE section ............................................14 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section...............................................................................................15 Updated OUTLINE DIMENSIONS .............................................16
Rev. G | Page 2 of 20
AD620 SPECIFICATIONS
Typical @ 25C, VS = 15 V, and RL = 2 k, unless otherwise noted. Table 1.
AD620A Parameter GAIN Gain Range Gain Error2 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1-1000 G = 1-100 Gain vs. Temperature Conditions Min G = 1 + (49.4 k/RG) 1 VOUT = 10 V Typ Max 10,000 0.03 0.15 0.15 0.40 VOUT = -10 V to +10 V RL = 10 k RL = 2 k 10 10 0.10 0.30 0.30 0.70 40 95 10 -50 125 185 1.0 1000 1500 2000 15 0.1 200 15 Min 1 0.01 0.10 0.10 0.35 10 10 AD620B Typ Max 10,000 0.02 0.15 0.15 0.50 40 95 10 -50 50 85 0.6 500 750 1000 7.0 0.3 400 30 Min 1 0.03 0.15 0.15 0.40 10 10 AD620S1 Typ Max 10,000 0.10 0.30 0.30 0.70 40 95 10 -50 125 225 1.0 1000 1500 2000 15 % % % % ppm ppm ppm/C ppm/C V V V/C V V V V/C Unit
VOLTAGE OFFSET Input Offset, VOSI Overtemperature Average TC Output Offset, VOSO Overtemperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Overtemperature Average TC Input Offset Current Overtemperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range3 Overtemperature
G=1 Gain >12 (Total RTI Error = VOSI + VOSO/G) VS = 5 V 30 to 15 V VS = 5 V to 15 V VS = 5 V 0.3 to 15 V VS = 15 V 400 VS = 5 V VS = 5 V to 15 V VS = 5 V 5.0 to 15 V VS = 2.3 V to 18 V 80 95 110 110 100 120 140 140 0.5 3.0 0.3 1.5
2.5
5.0
80 100 120 120 2.0 2.5 1.0 1.5
100 120 140 140 0.5 3.0 0.3 1.5 1.0 1.5 0.5 0.75
80 95 110 110
100 120 140 140 0.5 8.0 0.3 8.0 2 4 1.0 2.0
dB dB dB dB nA nA pA/C nA nA pA/C
10||2 10||2 VS = 2.3 V -VS + 1.9 to 5 V -VS + 2.1 VS = 5 V -VS + 1.9 to 18 V -VS + 2.1 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1
10||2 10||2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS + 2.1 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.3
10||2 10||2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4
G_pF G_pF V V V V
Overtemperature
Rev. G | Page 3 of 20
AD620
AD620A Parameter Conditions Min Typ Max Common-Mode Rejection Ratio DC to 60 Hz with 1 k Source Imbalance VCM = 0 V to 10 V G=1 73 90 G = 10 93 110 G = 100 110 130 G = 1000 110 130 OUTPUT Output Swing RL = 10 k VS = 2.3 V -VS + +VS - 1.2 to 5 V 1.1 Overtemperature -VS + 1.4 +VS - 1.3 VS = 5 V -VS + 1.2 +VS - 1.4 to 18 V Overtemperature -VS + 1.6 +VS - 1.5 Short Circuit Current 18 DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 1000 G = 10 800 G = 100 120 G = 1000 12 Slew Rate 0.75 1.2 Settling Time to 0.01% 10 V Step G = 1-100 15 G = 1000 150 NOISE Voltage Noise, 1 kHz Total RTI Noise = (e 2ni ) + (e / G)2
no
AD620B Min Typ Max Min
AD620S1 Typ Max
Unit
80 100 120 120
90 110 130 130
73 93 110 110
90 110 130 130
dB dB dB dB
-VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18
+VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5
-VS + 1.1 -VS + 1.6 -VS + 1.2 -VS + 2.3 18
+VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5
V V V V mA
0.75
1000 800 120 12 1.2 15 150
0.75
1000 800 120 12 1.2 15 150
kHz kHz kHz kHz V/s s s
Input, Voltage Noise, eni Output, Voltage Noise, eno
9 72 3.0 0.55 0.28 100 10 20 50 -VS + 1.6 1 0.0001 2.3 VS = 2.3 V to 18 V 0.9 1.1 -40 to +85
13 100
9 72 3.0 0.55 0.28 100 10 20 50 -VS + 1.6 1 0.0001 2.3 0.9 1.1 -40 to +85
13 100 6.0 0.8 0.4
9 72 3.0 0.55 0.28 100 10 20 50 -VS + 1.6 1 0.0001 2.3 0.9 1.1 -55 to +125
13 100 6.0 0.8 0.4
nV/Hz nV/Hz V p-p V p-p V p-p fA/Hz pA p-p k A V
RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100-1000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range4 Quiescent Current Overtemperature TEMPERATURE RANGE
For Specified Performance
f = 1 kHz
VIN+, VREF = 0
60 +VS - 1.6
60 +VS - 1.6
60 +VS - 1.6
18 1.3 1.6
18 1.3 1.6
18 1.3 1.6
V mA mA C
1 2
See Analog Devices military data sheet for 883B tested specifications. Does not include effects of external resistor RG. 3 One input grounded. G = 1. 4 This is defined as the same supply range that is used to specify PSR.
Rev. G | Page 4 of 20
AD620 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Internal Power Dissipation1 Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (Q) Storage Temperature Range (N, R) Operating Temperature Range AD620 (A, B) AD620 (S) Lead Temperature Range (Soldering 10 seconds) Rating 18 V 650 mW VS 25 V Indefinite -65C to +150C -65C to +125C -40C to +85C -55C to +125C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Specification is for device in free air: 8-Lead Plastic Package: JA = 95C 8-Lead CERDIP Package: JA = 110C 8-Lead SOIC Package: JA = 155C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. G | Page 5 of 20
AD620
Figure 4. Metallization Photograph. Dimensions shown in inches and (mm). Contact sales for latest dimensions.
Rev. G | Page 6 of 20
00775-0-004
AD620 TYPICAL PERFORMANCE CHARACTERISTICS
(@ 25C, VS = 15 V, RL = 2 k, unless otherwise noted.)
50 SAMPLE SIZE = 360 40
PERCENTAGE OF UNITS 2.0 1.5
INPUT BIAS CURRENT (nA)
1.0 0.5 0 -0.5 -1.0 -1.5 -I B
+IB
30
20
10
00775-0-005
0 -80 -40 0 40 80 INPUT OFFSET VOLTAGE (V)
-2.0 -75 -25 25 75 TEMPERATURE (C) 125 175
Figure 5. Typical Distribution of Input Offset Voltage
50 SAMPLE SIZE = 850 40
PERCENTAGE OF UNITS
Figure 8. Input Bias Current vs. Temperature
2.0
CHANGE IN OFFSET VOLTAGE (V)
1.5
30
1.0
20
0.5
10
0 -1200 -600 0 600 1200 INPUT BIAS CURRENT (pA)
00775-0-006
0
0
1
2 3 WARM-UP TIME (Minutes)
4
5
Figure 6. Typical Distribution of Input Bias Current
50 SAMPLE SIZE = 850 40
PERCENTAGE OF UNITS
Figure 9. Change in Input Offset Voltage vs. Warm-Up Time
1000
GAIN = 1
VOLTAGE NOISE (nV/ Hz)
100 GAIN = 10
30
20
10
10
GAIN = 100, 1,000 GAIN = 1000 BW LIMIT
0
-400
-200
0
200
400
00775-0-007
1 1 10 100 1k FREQUENCY (Hz) 10k 100k
INPUT OFFSET CURRENT (pA)
Figure 7. Typical Distribution of Input Offset Current
Figure 10. Voltage Noise Spectral Density vs. Frequency (G = 1-1000)
Rev. G | Page 7 of 20
00775-0-010
00775-0-009
00775-0-008
AD620
1000
CURRENT NOISE (fA/ Hz)
100
10
1
10
100 FREQUENCY (Hz)
1000
00775-0-011
Figure 11. Current Noise Spectral Density vs. Frequency
Figure 14. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100,000
TOTAL DRIFT FROM 25C TO 85C, RTI (V)
RTI NOISE (2.0V/DIV)
10,000
FET INPUT IN-AMP 1000
AD620A 100
00775-0-012
00775-0-014
TIME (1 SEC/DIV)
10 1k
10k
100k 1M SOURCE RESISTANCE ()
10M
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Figure 15. Total Drift vs. Source Resistance
160 140 120 100 G = 1000 G = 100 G = 10
RTI NOISE (0.1V/DIV)
CMR (dB)
G=1 80 60 40 20 0 0.1
00775-0-016
TIME (1 SEC/DIV)
00775-0-013
1
10
100 1k FREQUENCY (Hz)
10k
100k
1M
Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 16. Typical CMR vs. Frequency, RTI, Zero to 1 k Source Imbalance
Rev. G | Page 8 of 20
00775-0-015
AD620
180 160 140 G = 1000 120
PSR (dB)
35 G = 10, 100, 1000 30
OUTPUT VOLTAGE (V p-p)
25 G=1 20 15
100 80
G = 100
G = 10 60 40 20 0.1 G=1
00775-0-017
10 5 G = 1000 0 1k
BW LIMIT
G = 100 10k 100k FREQUENCY (Hz) 1M
00775-0-020
1
10
100 1k FREQUENCY (Hz)
10k
100k
1M
Figure 17. Positive PSR vs. Frequency, RTI (G = 1-1000)
Figure 20. Large Signal Frequency Response
180 160 140 120
PSR (dB)
+VS -0.0
INPUT VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES)
00775-0-018
-0.5 -1.0 -1.5
100 G = 1000 80 G = 100 60 G = 10 40 G=1 20 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M
+1.5 +1.0 +0.5
00775-0-021
-VS +0.0
0
5
10 15 SUPPLY VOLTAGE Volts
20
Figure 18. Negative PSR vs. Frequency, RTI (G = 1-1000)
1000
Figure 21. Input Voltage Range vs. Supply Voltage, G = 1
+VS -0.0
OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES)
-0.5 -1.0 -1.5 RL = 2k RL = 10k
100
GAIN (V/V)
10
+1.5 RL = 2k +1.0 +0.5 RL = 10k
00775-0-022
1
00775-0-019
0.1 100
1k
10k 100k FREQUENCY (Hz)
1M
10M
-VS +0.0
0
5
10 15 SUPPLY VOLTAGE Volts
20
Figure 19. Gain vs. Frequency
Figure 22. Output Voltage Swing vs. Supply Voltage, G = 10
Rev. G | Page 9 of 20
AD620
30
OUTPUT VOLTAGE SWING (V p-p)
VS = 15V G = 10 20
.... .... .... .... .... .... .... .... .... ....
10
.... .... .... .... .... .... .... .... .... ....
00775-0-026
0 0 100 1k LOAD RESISTANCE () 10k
00775-0-023
Figure 23. Output Voltage Swing vs. Load Resistance
Figure 26. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%)
.... .... .... .... .... .... .... .... .... ....
.... .... .... .... .... .... .... .... .... ....
.... .... .... .... .... .... .... .... .... ....
00775-0-024
.... .... .... .... .... .... .... .... .... ....
00775-0-027
Figure 24. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%)
Figure 27. Small Signal Response, G = 10, RL = 2 k, CL = 100 pF
.... .... .... .... .... .... .... .... .... ....
.... .... .... .... .... .... .... .... .... ....
.... .... .... .... .... .... .... .... .... ....
00775-0-025
.... .... .... .... .... .... .... .... .... ....
00775-0-030
Figure 25. Small Signal Response, G = 1, RL = 2 k, CL = 100 pF
Figure 28. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)
Rev. G | Page 10 of 20
AD620
20
.... .... .... .... .... .... .... .... ........
15
SETTLING TIME (s)
TO 0.01% TO 0.1%
10
.... .... .... .... .... .... .... .... ........
00775-0-029
5
0
0
5
10 OUTPUT STEP SIZE (V)
15
20
Figure 29. Small Signal Pulse Response, G = 100, RL = 2 k, CL = 100 pF
Figure 32. Settling Time vs. Step Size (G = 1)
1000
.... .... .... .... .... .... .... .... .... ....
SETTLING TIME (s)
100
10
.... .... .... .... .... .... .... .... .... ....
00775-0-030
1 1
10 GAIN
100
1000
Figure 30. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01% )
Figure 33. Settling Time to 0.01% vs. Gain, for a 10 V Step
.... .... .... .... .... .... .... .... ........
.... .... .... .... .... .... .... .... .... ....
.... .... .... .... .... .... .... .... ........
00775-0-031
.... .... .... .... .... .... .... .... .... ....
00775-0-034
Figure 31. Small Signal Pulse Response, G = 1000, RL = 2 k, CL = 100 pF
Figure 34. Gain Nonlinearity, G = 1, RL = 10 k (10 V = 1 ppm)
Rev. G | Page 11 of 20
00775-0-033
00775-0-032
AD620
10k * 1k 10T 10k INPUT 10V p-p
.... .... .... .... .... .... .... .... ........
100k VOUT
+VS 11k 1k 100 G=1 G = 100 G = 10 2 1 G = 1000 7
AD620
5 8 4 -VS 3
6
.... .... .... .... .... .... .... .... ........
00775-0-035
49.9
499
5.49k
*ALL RESISTORS 1% TOLERANCE
Figure 35. Gain Nonlinearity, G = 100, RL = 10 k (100 V = 10 ppm) Figure 37. Settling Time Test Circuit
.... .... .... .... .... .... .... .... ........
.... .... .... .... .... .... .... .... ........
00775-0-036
Figure 36. Gain Nonlinearity, G = 1000, RL = 10 k (1 mV = 100 ppm)
Rev. G | Page 12 of 20
00775-0-037
AD620 THEORY OF OPERATION
I1 20A VB 20A I2
A1 C1
A2 C2 10k
10k
A3 R3 400 R1 Q1 RG GAIN SENSE GAIN SENSE R2 Q2 R4 400 10k 10k +IN
OUTPUT REF
- IN
The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 38), yet offer 10x lower input bias current thanks to Supereta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 k, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then
-VS
Figure 38. Simplified Schematic of AD620
The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit.
00775-0-038
G=
49.4 k RG G-1
+1
RG =
49.4 k
Make vs. Buy: a Typical Bridge Application Error Budget
The AD620 offers improved performance over "homebrew" three op amp IA designs, along with smaller size, fewer components, and 10x lower supply current. In the typical application, shown in Figure 39, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of -40C to +85C. Table 3 shows how to calculate the effect various error sources have on circuit accuracy.
Rev. G | Page 13 of 20
AD620
Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy.
10V
10k * 10k *
Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by 2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error.
R = 350
R = 350
RG 499
OP07D
AD620A
REFERENCE
100 **
10k ** 10k **
OP07D
R = 350
R = 350
00775-0-040
AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX
OP07D
10k * 10k*
00775-0-039
PRECISION BRIDGE TRANSDUCER
Figure 39. Make vs. Buy
Table 3. Make vs. Buy Error Budget
Error Source ABSOLUTE ACCURACY at TA = 25C Input Offset Voltage, V Output Offset Voltage, V Input Offset Current, nA CMR, dB AD620 Circuit Calculation 125 V/20 mV 1000 V/100 mV/20 mV 2 nA x350 /20 mV 110 dB(3.16 ppm) x5 V/20 mV "Homebrew" Circuit Calculation (150 V x 2)/20 mV ((150 V x 2)/100)/20 mV (6 nA x350 )/20 mV (0.02% Match x 5 V)/20 mV/100 Total Absolute Error DRIFT TO 85C Gain Drift, ppm/C Input Offset Voltage Drift, V/C Output Offset Voltage Drift, V/C (50 ppm + 10 ppm) x60C 1 V/C x 60C/20 mV 15 V/C x 60C/100 mV/20 mV 100 ppm/C Track x 60C (2.5 V/C x 2 x 60C)/20 mV (2.5 V/C x 2 x 60C)/100 mV/20 mV Total Drift Error RESOLUTION Gain Nonlinearity, ppm of Full Scale Typ 0.1 Hz to 10 Hz Voltage Noise, V p-p 40 ppm 0.28 V p-p/20 mV 40 ppm (0.38 V p-p x 2)/20 mV Total Resolution Error Grand Total Error Error, ppm of Full Scale AD620 Homebrew 6,250 500 18 791 7,559 3,600 3,000 450 7,050 40 14 54 14,663 10,607 150 53 500 11,310 6,000 10,607 150 16,757 40 27 67 28,134
G = 100, VS = 15 V. (All errors are min/max and referred to input.)
Rev. G | Page 14 of 20
00775-0-041
"HOMEBREW" IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3ppm/C TRACKING **DISCRETE 1% RESISTOR, 100ppm/ C TRACKING SUPPLY CURRENT = 15mA MAX
AD620
5V
3 3k 3k G = 100 499 1 2 8
7
20k REF
AD620B
5 4
6 10k
IN
3k
3k
ADC AD705
20k AGND
DIGITAL DATA OUTPUT
1.7mA
1.3mA MAX
0.10mA
0.6mA MAX
00775-0-042
Figure 40. A Pressure Monitor Circuit that Operates on a 5 V Single Supply
Pressure Measurement
Although useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. Figure 40 shows a 3 k pressure transducer bridge powered from 5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement.
Medical ECG
The low current noise of the AD620 allows its use in ECG monitors (Figure 41) where high source resistances of 1 M or higher are not uncommon. The AD620's low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for batterypowered data recorders. Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance. The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm.
PATIENT/CIRCUIT PROTECTION/ISOLATION
+3V
C1
R1 10k R4 1M
R3 24.9k R2 24.9k
RG 8.25k
AD620A
G=7
0.03Hz HIGHPASS FILTER
G = 143
OUTPUT 1V/mV
OUTPUT AMPLIFIER
AD705J
00775-0-043
-3V
Figure 41. A Medical ECG Monitor Circuit
Rev. G | Page 15 of 20
AD620
Precision V-I Converter
The AD620, along with another op amp and two resistors, makes a precision current source (Figure 42). The op amp buffers the reference terminal to maintain good CMR. The output voltage, VX, of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load.
+VS VIN+ 7 + VX -
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total VOS for a given gain is calculated as Total Error RTI = input error + (output error/G) Total Error RTO = (input error x G) + output error
3 8 RG 1
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR.
00775-0-044
AD620
5 4 -VS Vx R1 [(V IN+ ) - (V IN- )] G R1 2
6 R1
VIN-
I
L
AD705
I L=
=
LOAD
INPUT PROTECTION
The AD620 features 400 of series thin film resistance at its inputs and will safely withstand input overloads of up to 15 V or 60 mA for several hours. This is true for all gains and power on and off, which is particularly important since the signal source and amplifier may be powered separately. For longer time periods, the current should not exceed 6 mA (IIN VIN/400 ). For input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an FD333) will reduce the required resistance, yielding lower noise.
Figure 42. Precision Voltage-to-Current Converter (Operates on 1.8 mA, 3 V)
GAIN SELECTION
The AD620's gain is resistor-programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 4 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ). For any arbitrary gain, RG can be calculated by using the formula:
RG =
49.4 k G -1
RF INTERFERENCE
All instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 43 demonstrates such a configuration. The filter limits the input signal according to the following relationship:
FilterFreq DIFF = FilterFreq CM = 1 2 R(2C D + C C )
To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TC--less than 10 ppm/C--for the best performance. Table 4. Required Values of Gain Resistors
1% Std Table Value of RG() 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 0.1% Std Table Value of RG( ) 49.3 k 12.4 k 5.49 k 2.61 k 1.01 k 499 249 98.8 49.3 Calculated Gain 2.002 4.984 9.998 19.93 49.91 100.0 199.4 501.0 1,003.0
1 2 RC C
where CD 10CC. CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R x CC will degrade the AD620's CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that CC is at least one magnitude smaller than CD. The effect of mismatched CCs is reduced with a larger CD:CC ratio.
Rev. G | Page 16 of 20
AD620
+15V 0.1 F 1 0 F
- INPUT +VS
AD648
R CC
100
+IN 499 -IN
+
R
CD
AD620
- REF
VOUT
100 -VS
RG
AD620
VOUT
CC
REFERENCE
00775-0-045
0.1 F -15V
1 0 F
+ INPUT -VS
Figure 43. Circuit to Attenuate RF Interference
Figure 44. Differential Shield Driver
COMMON-MODE REJECTION
Instrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 44 and Figure 45 show active data guards that are configured to improve ac common-mode rejections by "bootstrapping" the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.
+VS - INPUT RG 2
100
AD548
RG 2
AD620
VOUT REFERENCE
+ INPUT -VS
Figure 45. Common-Mode Shield Driver
GROUNDING
Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate "local ground." To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 46). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 46.
ANALOG P.S. +15V C -15V
DIGITAL P.S. C +5V
0.1 F
0.1 F
1F 1F 1F
+
AD620
AD585 S/H AD574A ADC DIGITAL DATA OUTPUT
Figure 46. Basic Grounding Practice
Rev. G | Page 17 of 20
00775-0-048
00775-0-047
00775-0-046
AD620
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying "floating" input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 47, Figure 48, and Figure 49. Refer to A Designer's Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications.
- INPUT +VS
RG
AD620
LOAD
VOUT
+ INPUT -VS
REFERENCE
+VS - INPUT
TO POWER SUPPLY GROUND
Figure 48. Ground Returns for Bias Currents with Thermocouple Inputs
RG
AD620
LOAD
VOUT
+VS - INPUT
+ INPUT -VS
REFERENCE
RG
AD620
LOAD
VOUT
TO POWER SUPPLY GROUND
00775-0-049
Figure 47. Ground Returns for Bias Currents with Transformer-Coupled Inputs
100k
+ INPUT 100k -VS
REFERENCE
00775-0-050
00775-0-051
TO POWER SUPPLY GROUND
Figure 49. Ground Returns for Bias Currents with AC-Coupled Inputs
Rev. G | Page 18 of 20
AD620 OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
5.00 (0.1968) 4.80 (0.1890)
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
8 5 4
4
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.060 (1.52) MAX 0.015 (0.38) MIN
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
SEATING PLANE 0.005 (0.13) MIN
0.015 (0.38) GAUGE PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 52. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8). Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
8
0.055 (1.40) MAX
5
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters)
Rev. G | Page 19 of 20
AD620
ORDERING GUIDE
Model AD620AN AD620ANZ2 AD620BN AD620BNZ2 AD620AR AD620ARZ2 AD620AR-REEL AD620ARZ-REEL2 AD620AR-REEL7 AD620ARZ-REEL72 AD620BR AD620BRZ2 AD620BR-REEL AD620BRZ-RL2 AD620BR-REEL7 AD620BRZ-R72 AD620ACHIPS AD620SQ/883B Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C Package Option1 N-8 N-8 N-8 N-8 R-8 R-8 13" REEL 13" REEL 7" REEL 7" REEL R-8 R-8 13" REEL 13" REEL 7" REEL 7" REEL Die Form Q-8
1 2
N = Plastic DIP; Q = CERDIP; R = SOIC. Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00775-0-12/04(G)
Rev. G | Page 20 of 20

▲Up To Search▲

Price & Availability of AD620SQ883B

	To Download AD620SQ883B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .